Mr P.Betts


Peter Betts

Download his C.V.


Proficient in the use of Hardware emulators, monitors and software simulators.
Proficient in the use of laboratory test equipment.
Used to working on my own initiative and without support.


Background Information

Peter has been in the communications marketplace since 1996 where he started work for Racal Communications working on military and industrial HF and VHF digital radios.

He was first introduced to GSM at NEC where he was primarily involved in integration of software modules onto NEC proprietary hardware using proprietary baseband and RF chipsets.

This extended from initially synchronising the mobile in time and frequency at the lowest levels within GSM physical layers, initial communication (RACH) with a basestation, generation of encoded speech and final transmission over the air interface on a dedicated traffic channel which was looped back to the mobile development platform and then decoded to produce speech output. (A physical layer 1 call was established)

This lead to further design work in 'C' of control scheduling for the mobile to establish true traffic channel communications with associated upper layer control.

Peter then moved to Hitachi Europe where he was involved in specifying the processing time and memory usage for a new chipset that would meet the requirements of standard GSM and also HCSD and EDGE performance.

He wrote functional specifications, design and implementation requirements for the channel codecs (encoding and decoding) using both written document and structured design and analysis techniques. This included FIRE codecs (block coders), convolutional encoding, convolutional decoding using Viterbi techniques, interleaving and timeslot burst building (anything required for the associated control channel processing)

Finally Peter moved to Nokia Networks where he has been involved in the design of the downlink channel encoders for EDGE general packet radio (EGPRS) data coding schemes MCS1->9. CRC parity generation, convolutional encoding, bit puncturing, interleaving, burst mapping and bit swapping.

He has also been involved in the test and integration of the downlink EGPRS channel encoders and uplink channel decoders which take soft decision samples from the receiver unit and de-convolves them using either a software Viterbi unit or the proprietary viterbi hardware acceleration unit to generate hard decision bits.

Peter then moved back to Hitachi to design and implement EDGE channel codecs.

Peter has also been working for TRL Performance designing engine management systems, particularly for engine tuning and racing. He has concentrated on designing the electronics and writing the embedded software for a number of monitoring and modifying units used in the tuning process. This includes writing graphical user interfaces for LCD displays, writing low level display drivers, low level interface routines to communicate via RS232 and CAN-bus drivers and controllers and signal processing software using his skills in Digital Signal Processing.

Peter has attended training on CAN-bus (ISO-11898 and SAE J1939) and OBD (Diagnostics On CAN) ISO-15765 to help with the development with future products.

Peter nows manages THOR Racing full time and offers bespoke elecronics and software development for the Automotive industry.

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